PROJECT JANUS MINI (16-TILE): MULTI-PHYSICS CO-SIMULATION & SYSTEM VERIFICATION SPECIFICATION

Document ID: JANUS-SIM-SPEC-MINI16-2026-V1
Target Hardware: JANUS Mini 16-Tile Monolithic Planar MVP (Model 1A)
Classification: Engineering Blueprint / Verification Standard
Lead Architect: Deepanshu Bhardwaj
Status: Approved for Implementation

1. Executive Summary & Verification Objective

The objective of this specification is to define the end-to-end, multi-scale, multi-physics co-simulation framework for the JANUS Mini 16-Tile Accelerator (Model 1A).

To bridge the gap between nanophotonic Maxwell field physics and high-level artificial intelligence inference, this framework couples open-source, high-performance simulation engines into an automated, single-command validation pipeline.

+---------------------------------------------------------------------------------------------------+
|                        JANUS MINI 16-TILE MULTI-SCALE VERIFICATION STACK                          |
+---------------------+-----------------------+-----------------------------------------------------+
| Simulation Tier     | Engine / Toolchain    | Primary Physical / Architectural Scope              |
+---------------------+-----------------------+-----------------------------------------------------+
| Tier 1: Optics      | 3D MEEP (FDTD)        | Maxwell solver, GST-467 S-matrix, field absorption |
| Tier 2: Thermal     | Elmer FEM (3D FEM)    | Transient Z-axis heat diffusion, SiO2 buffer, ROM   |
| Tier 3: Circuit     | Xyce (Parallel SPICE) | SAC2M APD, StrongARM latches, 100 GHz eye diagrams  |
| Tier 4: RTL Logic   | Cocotb + Verilator    | Gate-level CRT adder tree (210 ps), RNS encoders    |
| Tier 5: Arithmetic  | Python RNS Engine     | Spatial One-Hot, JIR scheduler, RRNS, Z3 proofs     |
+---------------------+-----------------------+-----------------------------------------------------+

2. Global Simulation Constants & Variable Registry

All simulation parameters defined in this section are immutable constants shared across all five verification tiers. Every variable is assigned a canonical Python identifier (used directly in simulation code), a mathematical symbol, a fixed numerical value, SI-compatible unit, and tier scope indicating which simulation tiers consume it.

Tier Scope Key: T1 = MEEP Optics | T2 = Elmer Thermal | T3 = Xyce Circuit | T4 = Cocotb RTL | T5 = Python RNS

2.1 Universal Physical Constants

2.2 Operating Wavelength, Laser Source & Optical Carrier

2.3 Optical Material Refractive Indices & Electro-Optic Coefficients

2.4 Phase-Change Material (Ge4Sb6Te7 / GST-467) Properties

2.5 Waveguide & Photonic Cell Geometry

2.6 Mini 16-Tile Architectural Topology

2.7 Die Geometry & Z-Axis Physical Stack (Mini 16-Tile Planar)

2.8 Heat Spreader & Package Dimensions

2.9 Thermal Material Properties -- Silicon (CMOS Substrate)

2.10 Thermal Material Properties -- SiO2 (Thermal Buffer)

2.11 Thermal Material Properties -- Copper (TDVs, Heat Spreaders)

2.12 Thermal Material Properties -- Germanium (APD Absorption Layer)

2.13 Thermal Material Properties -- Air (Package Voids)

2.14 Thermal Material Properties -- LiTaO3 (Pockels Modulators)

2.15 Thermal Dynamics, JIR Scheduling & Temperature Budgets

2.16 SAC2M Ge/Si Avalanche Photodetector Parameters

2.17 Receiver Electronics & Decision Logic

2.18 Receiver Sensitivity, BER & Detection Margin

2.19 Laser Optical Power & Electrical Power (Mini 16-Tile)

2.20 Optical Distribution Loss Budget (Mini 16-Tile)

2.21 System Electrical Power Budget (Mini 16-Tile)

2.22 Timing, Frequency & Latency Budget

2.23 RNS Arithmetic & Moduli Configuration

2.24 Throughput & Energy Efficiency (Mini 16-Tile)

2.25 PCM Reconfiguration & Transient Power

2.26 Nonlinear Optics & Spectral Purity

2.27 Analog SNR & Precision Limits (Reference Comparisons)

2.28 Logarithmic & Unit Conversion Constants

3. Target Hardware Baseline: JANUS Mini 16-Tile (Model 1A)

The simulation suite strictly targets the verified hardware parameters of the JANUS Mini 16-Tile Planar Monolithic Accelerator:

4. Five-Tier Multi-Physics Co-Simulation Pipeline

+---------------------------------------------------------------------------------------------------+
|                        JANUS MINI 16-TILE DATA HANDOFF & SIMULATION FLOW                          |
+---------------------------------------------------------------------------------------------------+

   [ TIER 1: 3D MEEP FDTD ]
   | - Solves GST-467 cell (a-GST vs c-GST), TFLN crossing, and 1x256 Pockels router
   | - Exports: S-parameters (Touchstone format) & Volumetric Optical Absorption Q_opt(x,y,z)
   v
   +-- S-Parameters (Touchstone .s4p) ----------+
   |                                            v
   |                                 [ TIER 3: XYCE SPICE ]
   |                                 | - Vector-fitting (vectfit) to passive subcircuit
   |                                 | - SAC2M APD equivalent circuit (M=7, C_j=0.8 fF)
   |                                 | - StrongARM dynamic latch model (~100 aJ/event)
   |                                 | - Outputs: 100 GHz Eye Diagrams, Jitter, BER <= 10^-18
   v                                 v
   [ TIER 2: ELMER FEM THERMAL ]     | Realistic BER & Transit Delays
   | - 3D transient heat diffusion   |
   | - Imports Q_opt(x,y,z) + CMOS   |
   | - Validates tau_diff = 69.06 ms |
   | - Exports: Reduced-Order Model  |
   v                                 |
   +-- Dynamic Thermal ROM Matrix ---+-----------------------------+
   |                                 v                             v
   |              [ TIER 4: DIGITAL RTL (COCOTB + VERILATOR) ]     |
   |              | - Gate-level RNS Modulo Front-End               |
   |              | - Pipelined CRT Adder Tree (210 ps)             |
   |              | - Evaluates CMOS propagation & clock power       |
   |              v                                                |
   |              +-- Gate Delays & Latency -----------------------+
   |                                                               v
   +-----------------------------------------------------> [ TIER 5: PYTHON RNS ENGINE ]
                                                           | - Spatial One-Hot Tensor Routing
                                                           | - JIR Dynamic Thermal Scheduler
                                                           | - RRNS Fault Self-Healing
                                                           | - Z3 SMT Formal Proofs
                                                           | - Exact INT4-INT64 GEMM Benchmarking
                                                           v
                                                           [ VERIFIED EXACT ACCELERATOR ]

Tier 1: Electro-Optics & FDTD Extraction (3D MEEP)

A. Target Unit-Cell Geometries

1. GST-467 Phase-Change Directional Coupler Switch:
2. Silicon core (wg_width_si=450 nm x wg_height_si=220 nm), SiO2 cladding (n_sio2=1.444).
3. Active Ge4Sb6Te7 patch (gst_patch_thickness=15 nm, A_pcm_cell=1.25 um^2 relaxed cell area).
4. Solves at lambda_0=1064 nm in both states:
   • Amorphous (a-GST): n_gst467_amorph=3.45 + i*k_gst467_amorph=0.008 (Low-loss cross state).
   • Crystalline (c-GST): n_gst467_cryst=4.20 + i*k_gst467_cryst=0.18 (High-index bar state).
5. Ultra-Low-Loss Waveguide Crossing Matrix:
6. Multi-mode interference (MMI) optimized crossing (IL_crossing < 0.02 dB, XT_crossing < -40 dB).
7. LiTaO3 Pockels Input Modulator Cell:
8. Thin-film lithium tantalate (r33_litao3=30.5 pm/V) with sub-E_pockels_switch=50 aJ/switch energy.

B. Extracted Deliverables

• Scattering Matrix (Touchstone .s4p format): Insertion loss (IL_switch_cell <= 0.10 dB), extinction ratio (ER_pcm_switch >= 25 dB), phase response, and group delay.
• Volumetric Heat Density Map (Q_opt(x,y,z)): Exported to HDF5 grid using the formula:
  Q_opt(x,y,z) = (1/2) * omega_optical * epsilon_0 * Im[eps_r(x,y,z)] * |E(x,y,z)|^2

Tier 2: 3D Multi-Stratum Thermal Stack Analysis (Elmer FEM)

A. Geometric Domain & Material Properties

• CMOS Base Substrate: h_cmos=50 um Silicon (k_si_thermal=148 W/(m-K), rho_si=2330 kg/m^3, cp_si=705 J/(kg-K)).
• Monolithic SiO2 Thermal Buffer: h_sio2_buffer=250 um fused silica (k_sio2_thermal=1.38 W/(m-K), rho_sio2=2200 kg/m^3, cp_sio2=703 J/(kg-K), alpha_sio2=9.05 x 10^-7 m^2/s).
• SiPh Core Stratum: h_siph=30 um active photonics + Cu Through-Dielectric Vias (TDVs).
• Boundary Conditions: Top surface convection/conduction to Heat Spreader (HS1, T_ambient=25 deg-C), lateral adiabatic boundaries.

B. Verification Targets

1. Thermal Diffusion Time Constant: Verify tau_diff = h_sio2_buffer^2 / alpha_sio2 = 69.06 ms = 13,812 JIR cycles.
2. Per-Cycle Thermal Rise: Verify delta_T_cycle <= 0.80 mK per tau_jir=5 us JIR computational epoch.
3. Non-Volatile Retention Guard: Ensure T_max_operating < 70 deg-C (much less than T_crystallization_guard=150 deg-C).
4. Thermal ROM Extraction: Export state-space Foster/Cauer RC thermal impedance matrices for the Python JIR scheduler.

Tier 3: Circuit & Signal Integrity Co-Simulation (Xyce SPICE)

A. Subcircuit Network Composition

1. Passive Optical Backbone: MEEP S-parameter Touchstone files fitted to passive, causal SPICE subcircuits using rational vector-fitting (vectfit).
2. SAC2M Ge/Si Avalanche Photodetector:
3. Equivalent circuit with primary photocurrent I_ph = R_responsivity * P_opt (R_responsivity=0.8 A/W at lambda_0=1064 nm).
4. Avalanche gain multiplication M_apd=7.
5. Junction capacitance C_j_apd=0.8 fF, series resistance R_s_apd=25 ohm.
6. Excess noise factor F_excess_noise=2.0 with ionization ratio k_ionization=0.06.
7. StrongARM Regenerative Comparator:
8. Clocked sensing latch consuming E_strongarm=100 aJ/event, regeneration time t_regen <= 3.5 ps.

B. Verification Targets

1. Eye Diagram Opening: Open eye at f_clk=100 GHz optical rate (T_cycle=10 ps cycle period).
2. Bit Error Rate (BER): Verify BER_target <= 10^-18 under practical sensitivity P_sens_practical=-23.21 dBm with link_margin=+4.61 dB at P_det=-18.59 dBm.

Tier 4: Digital CMOS RTL & Timing Verification (Cocotb + Verilator)

A. Synthesized Digital Blocks

1. High-Speed RNS Modulo Front-End: Decomposes input integers X into x_i = X mod m_i across N_tiles=16 parallel residue channels (m_i <= m_max=256).
2. Pipelined Chinese Remainder Theorem (CRT) Adder Tree:
3. N_crt_pipeline_stages=4 stage pipelined modulo adder tree reconstructing 64-bit integer values from 16 residue channels.
4. Total digital reconstruction latency t_crt <= 210 ps.
5. JIR Consistency & Fault Monitor: Monitors strongARM column outputs for RRNS parity violations.

B. Verification Targets

• Cycle-accurate co-simulation linking Python testbenches to compiled Verilog logic with zero clock cycle slips.

Tier 5: Algorithmic Exactness, JIR & RRNS Verification (Python Engine)

A. Core Python Modules

1. moduli_generator.py: Generates coprime sets M = {m_1, ..., m_16} with m_i <= m_max=256, satisfying dynamic range prod(m_i) > 2^64.
2. formal_verifier.py: Uses the Z3 SMT Solver to mathematically prove that finite field multiplication in Z_(m_i) is isomorphic to the 4-stage binary tree routing states without edge-case failures.
3. one_hot_router.py: Simulates spatial 1-hot tensor contractions (N_dim=32 x 32 matrices across N_tiles=16 tiles) with zero floating-point rounding.
4. jir_scheduler.py: Emulates microsecond-level closed-loop tile temperature tracking using the Elmer thermal ROM matrix, executing dynamic tile rotation within tau_jir=5 us.
5. rrns_fault_engine.py: Injects stochastic physical bit errors (from Xyce BER models) and executes single-channel residue projection self-healing with N_rrns_redundant=2 redundant channels.
6. gemm_validator.py: Executes standard INT4, INT8, INT16, INT32, INT64 matrix multiplication benchmarks and performs bit-exact comparison against NumPy / PyTorch 64-bit ground truth.

5. Quantitative Pass / Fail Verification Criteria

To achieve full engineering sign-off for the JANUS Mini 16-Tile model, the unified simulation suite must satisfy the following numerical bounds:

6. Directory Architecture & Modular Workspace Layout

janus_mini16_sim/
+-- configs/
|   +-- mini_16t_constants.py         # ALL Section 2 global variables as Python constants
|   +-- mini_16t_specs.json           # JSON export of constants for cross-tool interop
+-- tier1_meep_optics/
|   +-- gst467_switch_cell.py         # 3D FDTD of PCM directional coupler
|   +-- waveguide_crossing.py         # MMI crossing extraction
|   +-- litao3_pockels_router.py      # LiTaO3 Pockels micro-ring modulator
|   +-- export_touchstone.py          # Generates Touchstone .s4p files
|   +-- export_heat_map.py            # Exports Q_opt(x,y,z) to HDF5
+-- tier2_elmer_thermal/
|   +-- mini16_mesh.geo               # Gmsh 3D stack geometry (330 um)
|   +-- materials.sif                 # Elmer material property definitions
|   +-- case.sif                      # Elmer solver input file (transient heat)
|   +-- extract_thermal_rom.py        # Extracts Foster/Cauer RC network
+-- tier3_xyce_circuit/
|   +-- vector_fit_s_params.py        # Rational fitting for SPICE subcircuits
|   +-- sac2m_apd_model.cir           # Ge/Si SAC2M equivalent circuit
|   +-- strongarm_latch.cir           # StrongARM regenerative comparator
|   +-- run_eye_diagram.cir           # 100 GHz transient eye diagram & BER
+-- tier4_rtl_digital/
|   +-- rns_encoder.v                 # Modulo decomposition logic
|   +-- crt_adder_tree.v              # 210 ps pipelined CRT reconstruction
|   +-- jir_fault_monitor.v           # RRNS parity violation detector
|   +-- test_crt_cocotb.py            # Cocotb testbench with Verilator
+-- tier5_python_rns/
|   +-- moduli_generator.py           # 16-channel coprime dynamic range
|   +-- formal_verifier.py            # Z3 SMT formal proof
|   +-- spatial_one_hot_router.py     # 4-stage 16-Tree Fermat Core tensor contraction
|   +-- jir_thermal_scheduler.py      # Microsecond tile rotation engine
|   +-- rrns_self_healing.py          # Single-fault parity recovery
|   +-- gemm_exact_benchmark.py       # Bit-exact GEMM validation vs FP32/INT64
+-- run_mini16_full_cosim.py          # Master orchestrator executing Tiers 1-5
+-- README.md                         # Setup instructions & dependencies

Specification approved for Project JANUS Mini 16-Tile hardware realization and validation suite execution.